1. Field of the Invention
The present invention relates to a technology for a multi-core model simulation for performing a simulation of inter-core-model communication in a multiprocessor and a system-on-a-chip (SoC) model.
2. Description of the Related Art
The recent trend has been for a central processing unit (CPU) to shift to a multi-core processor. In addition to a general-purpose CPU, an embedded type CPU has been shifting to the multi-core processor. To reduce a development period of a system large-scale integration (LSI), which has been becoming increasingly complicated, it is important to co-design hardware and software in an early stage of the design. However, a conventional simulator cannot support the multi-core processor. In addition, a simulation speed of the conventional simulator is not sufficiently high. Therefore, development of a high-speed software-hardware-coordinated simulator has been demanded.
A conventional multi-processor model simulator is explained with two processor models PE1 and PE2 having a core model as an example. FIG. 1 is a flowchart of a simulation in a conventional multi-processor model and FIG. 2 is a timing chart of the simulation.
First, it is determined whether to perform a simulation on a target program (step S2201). If it is determined not to perform the simulation (“NO” at step S2201), the process is finished. On the other hand, if it is determined to perform the simulation (“YES” at step S2201), variables are specified (step S2202) and a core-model processing of the processor model PE1 is executed (step S2203). Specifically, the specified variables are sequentially applied to an instruction execution function of the processor model PE1 to execute the core-model processing of the processor model PE1.
When the core-model processing of the processor model PE1 is completed, the specified variables are sequentially applied to an instruction execution function of the processor model PE2 to execute the core-model processing of the processor model PE2 (step S2204). When the core-model processing of the processor model PE2 is completed, one loop of the simulation is completed. Then, the processing proceeds to step S2201. As shown in FIG. 2, the processing is executed in the order of the processor model PE1, processor model PE2, processor model PE1, processor model PE2, . . . .
The execution processing of the core model processing of the processor model PE1 (step S2203) is specifically described. It is determined whether there is an unexecuted instruction (step S2211). If there is no unexecuted instruction (“NO” at step S2211), the process proceeds to the core model execution processing of the processor model PE2 (step S2204).
On the other hand, if there is an unexecuted instruction (“YES” at step S2211), the unexecuted instruction is fetched (step S2212) and executed (step S2213). It is then checked whether an interruption processing has been performed (step S2214), and the processing returns back to step S2211.
In the core model execution processing of the processor model PE2 (step S2204), it is determined whether there is an unexecuted instruction (step S2221). If there is no unexecuted instruction (“NO” at step S2221), the process proceeds to step S2201.
On the other hand, if there is an unexecuted instruction (“YES” at step S2221), the unexecuted instruction is fetched (step S2222) and executed (step S2223). It is then checked whether an interruption processing has been performed (step S2224), and the process returns goes back to step S2221.
In this simulator, since the multi-processor model sequentially executes instruction execution of one core for each core, a communication processing between the cores (inter-core-model communication) is performed when instruction execution of a core is completed and while instruction execution of the next core is performed. If an interruption to the processor model PE2 is detected at step S2214 of the processor model PE1, communication from the processor model PE1 to the processor model PE2 is performed to temporarily execute the core model processing of the processor model PE2. Such a technology is disclosed in, for example, Japanese Patent Application Laid-Open Publication Nos. H5-35534, H4-352262 and 2001-256267.
However, in a conventional simulation mode described above, since execution processing (step S2203, step S2204) of processor models PE1 and PE2 is serialized, the simulation time is increased more and more.
Since execution processing (step S2203, step S2204) of processor models PE1 and PE2 is serialized, if the interruption processing is performed in the processor model PE1 for the processor model PE2, the core model processing of the processor model PE2 can be temporarily executed by performing inter-core-model communication with the processor model PE2.
If interruption processing is performed in the processor model PE2 for the processor model PE1, since an instruction to be executed by the interruption has already been finished in the processor model PE1, communication cannot be performed with the processor model PE1. Therefore, it is necessary to wait until the instruction execution of the processor model PE1 in the next loop. As a result, the simulation time further increases.
Although a multi-processor model is used in a technology disclosed in Japanese Patent Application Laid-Open Publication No. 1993-35534, the inter-core-model communication is not synchronized between processor models. Consequently, similarly to the conventional simulator shown in FIG. 1 and FIG. 2, the simulation time increases.
Thus, in the conventional simulator, due to the increase of the simulation time, a speed of the simulation is reduced. As a result, a development period for a device that includes the target program is delayed.